A phase-locked loop (hereinafter referred to as a “PLL”) is now an indispensable element in a semiconductor integrated circuit system and is included in almost all LSIs. Also, there are broad ranges of applications of PLLs extending over various fields such as communications equipment, microprocessors and IC cards.
FIG. 32 shows the architecture of a general charge pump type PLL. The outline of the PLL will now be described with reference to this drawing. A phase comparator 10 compares an input clock CKin supplied to the PLL with a feedback clock CKdiv so as to output an up signal UP and a down signal DN in accordance with a phase difference between these clocks. A charge pump circuit 20 outputs a charge current Ip on the basis of the up signal UP and the down signal DN. A loop filter 30 smoothes the charge current Ip so as to output a voltage Vout. A voltage controlled oscillator 40 changes the frequency of an output clock CKout of the PLL on the basis of the voltage Vout. An N frequency divider 50 divides the output clock CKout in the frequency by “N” so as to feedback the divided clock to the phase comparator 10 as the feedback clock CKdiv. While these operations are repeated, the output clock CKout is gradually converged into a desired frequency to be locked.
Among the above-described elements of the PLL, the loop filter 30 is particularly significant. It can be said that the response characteristic of the PLL is determined depending upon the filtering characteristic of the loop filter 30.
FIG. 33 shows general loop filters. The passive filter shown in FIG. 33(a) has a disadvantage that its characteristic is changed when another circuit is connected at a subsequent stage. When the filter is varied to be active in order to overcome this disadvantage, the active filter shown in FIG. 33(b) is obtained. The transfer characteristics of these filters are equivalent. Thus, the loop filter 30 is generally realized by a low-pass filter constructed from a combination of a resistive element R and a capacitive element C.
In the control theory for the PLL, the response bandwidth of the PLL is preferably set to a frequency approximately 1/10 of that of an input clock at most. According to this theory, in a PLL accepting, as an input, an input clock of a comparatively low frequency, it is necessary to lower the cut-off frequency of the loop filter so as to narrow the response bandwidth. Therefore, a loop filter used in a conventional PLL has a comparatively large time constant, namely, a large CR product. In order to realize a large CR product, a large-scale capacitive element is generally used.
On the other hand, the response speed of a PLL depends upon its dumping factor. The dumping factor is changed in accordance with the frequency of the input clock to the PLL, and is preferably kept constant in order to stabilize the response characteristic of the PLL. Therefore, in a conventional PLL accepting, as an input, an input clock of a wide-band frequency, the dumping factor is controlled by using a loop filter variable in its filtering characteristic.
FIG. 34 shows a conventional loop filter variable in its filtering characteristic. The loop filter of FIG. 34(a) includes resistor ladder circuits 100. The resistor ladder circuit 100 includes, as shown in FIG. 34(b), a large number of resistors and switches, so as to provide a variety of resistance values by appropriately controlling the switches. In general, a loop filter including such a resistor ladder circuit 100 is used in the PLL.
Alternatively, FIG. 35 shows another example of the conventional loop filter variable in its filtering characteristic. The loop filter 30 shown in FIG. 35 includes an integrator 30-1, an inverting amplifier 30-2 and an adder 30-3. The integrator 30-1 integrates a charge current Ip1 output from a first charge pump circuit 20a so as to output a smoothed voltage. The inverting amplifier 30-2 inverts and amplifies a charge current Ip2 output from a second charge pump circuit 20b. The adder 30-3 adds the output of the integrator 30-1 and the output of the inverting amplifier 30-2 so as to obtain an output voltage of the loop filter 30. In such a loop filter 30, the dumping factor of the PLL can be adjusted by appropriately changing the ratio between the charge current Ip1 and the charge current Ip2 (as described in, for example, Japanese Patent No. 2778421).
As described above, in a PLL accepting, as an input, an input clock of a comparatively low frequency, a capacitive element with a large size is used in order to attain a large CR product of the loop filter. Furthermore, in a PLL accepting, as an input, an input clock of a wide-band frequency, it is necessary to provide the resistor ladder circuit as shown in FIG. 34 or a plurality of charge pump circuits and operational amplifiers as shown in FIG. 35 for adjusting the dumping factor. All of these cases are factors to increase the circuit scale.
In some application products of PLLs that are difficult to externally provide a large capacitive element, it is significant to reduce the circuit area of the PLL. In an IC card in particular, elements with a size larger than the thickness of the card should not be included from the viewpoint of the reliability. Accordingly, it is substantially impossible to externally provide a large capacitive element on an IC card, and hence, the circuit area reduction of the PLL is a problem to be indispensably solved. This also applies to an LSI in which a PLL is mounted on a pad region.
Also, in an LSI having a chip-on-chip structure, a PLL included in the upper chip is preferably smaller. Furthermore, since a large number of PLLs are used in a microprocessor, the circuit area of the PLLs largely affects the circuit area of the whole microprocessor.